The present invention relates to a static induction semiconductor device of the type used for electrical apparatuses such as a power conversion apparatus, and a method and a drive circuit for the static induction semiconductor device.
In accordance with a need for largely increasing the power and the frequency in a power conversion apparatus, it has been desired to develop a low power loss semiconductor switching element having a high speed performance in addition to a large controllable current. To achieve such a device, the following two approaches are possible.
One of them is to further improve further the performance of a conventional semiconductor chip made of silicon, which is most widely used now, by re-examining the structure of the chip or a combination of the structure and operational mechanisms thereof. Although this approach has the advantage that is easy to improve the performance of the chip since it is possible to make use of established high level fabrication processing techniques for manufacture of a semiconductor chip and a large amount of knowledge concerning semiconductor technology, this approach has a problem in that a large improvement in the performance of the semiconductor chip can not be expected, since the performance of the chip is restricted by theoretical limits in the physical properties of silicon.
Another of the two approaches is to realize a semiconductor power chip a which the performance exceeds a performance limit of a silicon chip by far, the limit being due to the physical limits of silicon. For example, it is disclosed in a paper: "IEEE Electron Device Letters, Vol. 10, No. 10, pp. 455-457 (1989)" that the performance of a chip made of silicon carbide (hereafter referred to as SiC) is more than 1000 times of that of a silicon chip. The reason why an excellent performance of a power chip can be realized by using SiC is that the avalanche breakdown potential of SiC is high. For instance, the avalanche breakdown potential of SiC is approximately 10 times higher than that of silicon. In a paper: "IEEE Transaction of Electron Devices, Vol. 40, No. 3, pp. 645-655 (1993)", it is disclosed that the electric resistance of a drift layer in a chip made of SiC can be reduced by about two figures. Thus, a chip using SiC is regarded as a very promising chip since it can reduce power loss occurring at the time of turn-on of the semiconductor chip.
In at developing a next generation semiconductor power chip using SiC, it is desirable if the semiconductor chip is a unipolar type chip. This is because it can be expected that a large capacity device satisfying all of the three fundamental conditions of high-speed operation, a low power loss, and a voltage control device, can be realized by a unipolar type device using SiC.
A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a typical unipolar type switching element. However, problems in a MOSFET using SiC have become clear recently. Since the mobility of electrons in an inversion layer is small in the structure of a DMOS (Double Diffusion MOS) in which a p-type base layer is formed by ion injection, it is difficult to make use of the advantage of the low resistance in a drift layer of the MOSFET. In a trench MOS structure, since the insulation ability of a trench SiO.sub.2 is not sufficient, dielectric breakdown occurs at an oxide film before the avalanche breakdown of the SiC layer occurs. Further, it is reported in a paper: "Proc. of ISPSD, pp. 119-122, May (1996)" that if the thickness of a drift layer is made thicker so that the potential at an interface between a SiC layer and an oxide film does not exceed the critical potential of the oxide film, the ON-resistance becomes very large.
Another example of a unipolar type switching element is a Static Induction Transistor (hereafter referred to as a SIT). Since a SIT is one kind of a junction-type FET, it is possible to avoid the above-mentioned problems of the low electron mobility in the interface at the oxide film and low insulation withstand voltage of the oxide film.
In the following, the structure and the operation of a SIT will be briefly explained with reference to FIG. 2. In a semiconductor substrate 200 in which a SIT shown in FIG. 2 is formed, for example, a drift region 212 is formed by growing a n-type epitaxial growth layer of a lower impurity concentration than that in a n-type drain region 211 on the upper surface of the drain region 211 of a high impurity concentration. Further, a pair of p-type gate regions 213 of a comparatively deep island shape are formed from the surface of the substrate 210 into the drift region 212, and a n-type source region 214 of a high impurity concentration are formed at the surface of the drift region 212 between the pair of gate regions 213. Furthermore, a drain terminal D, a gate terminal G, and a source terminal S, are connected to a drain electrode 225 provided on the drain region 211; a gate electrode 226 is provided on the gate regions 213; and a source electrode 227 is provided on the source region 214, respectively. At an OFF state of this SIT, a reverse bias is applied between the source and the gates, and a depletion layer extends from a p-n junction between each of the gate regions 214 and the drift region 212, mainly into the drift region 212. Therefore, a potential barrier of electrons is generated in a channel region in which current flows between the source and the drain, the channel being formed in the drift region 212 between the pair of the gate regions 213, and the voltage between the source and the drain can be blocked by the potential barrier.
In producing a SIT made of SiC, it is necessary to form more minute gates than those in a SIT made of Si in order to obtain a high blocking gain. This is due to the following two reasons. One reason is that, since thermal diffusion driving-in of dopants is difficult for SiC, a deep gate layer is hardly formed in a SiC substrate. The other reason is that, since the impurity concentration of a drift layer is high, a channel region of a depletion layer is scarcely pinched-off.
In a SIT made of SiC, while the resistance of a drift layer can be decreased, since, processing of minute gates is required, it happens that the yield of the chips decreases, or the ON resistance increases, notwithstanding the use of SiC.
As a method of reducing the ON resistance of a conventional SIT having minute gates, a method in which the ON voltage is reduced by applying a forward bias to the gates of a SIT is disclosed in a document: "IEDM Tech. Dig., pp. 676-679 (1978)".A SIT to which the above-mentioned method is applied is called a Bipolar mode SIT (hereafter referred to as BSIT). In a BSIT, by adopting a conductivity modulation method in which holes of minority carriers are injected from a gate region to a drift region, the resistance of the drift region is decreased.
While a SIT is a voltage drive type element, since a BSIT is a current drive type element, a BSIT needs a large drive power. Further, a BSIT has a problem that the turning-off time and the turning loss increase by the accumulation of the minority carriers.